- 시뮬레이션을 이용한 웨이퍼 FAB 공정에서의 병목 공정 탐지 프레임워크
- ㆍ 저자명
- 양가람,정용호,김대환,박상철,Yang. Karam,Chung. Yongho,Kim. Daewhan,Park. Sang Chul
- ㆍ 간행물명
- 한국CAD/CAM학회논문집
- ㆍ 권/호정보
- 2014년|19권 3호|pp.214-223 (10 pages)
- ㆍ 발행정보
- 한국CAD/CAM학회
- ㆍ 파일정보
- 정기간행물| PDF텍스트
- ㆍ 주제분야
- 기타
This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.