When the input of synchronizer which is used for the purpose of synchronizing the master clock of computer with the interrupt system, a sort of random variable device, is gated with asynchronous intersection of the fall time of the master clock and the risetime oi the interrupt request, synchronizer is drived in Metastable region. This paper is presented circuit analysis of Metastable phenomena and analysis for transient process from metastable point to stable state, and also realities the collect logic with Inverter and open collector methods with a view to improving logic failure caused by the mishappen phenomena.