This paper reports the performance and reliability of both n-and p-channel MOSFETs with ultrathin$(65^{circ}C)$ LPCVD gate oxides annealed in $N_2$ ambinet as compared to MOSFETs with thermal gate oxides. It is shown than n-and p-MOSFETs with CVD gate oxides ahve better initial device performance ($higher;g_m$, current dirivability, and effective electron and hole mobilities) and enhanced device reiability(${Delta}g_{m}$, ${Delta}V_{th}$ and stress-induced GIDL enhancement) than the MOSFETs with thermal gate oxides. Furthemore, signigicantly improved time-dependent dielectric breakdown characteristics of CVD gate oxide has been demonstrated. Strainless CVD $SiO_2$ after proper post-deposition annealing and the film formation mechanism(deposited-on rather than grown from the substrate) are speculated to results in the improvements in performance and reliability of CVD oxide devices.