As device sizes are scaled down to submicron dimensions, planarization technology becomes increasingly important for both device fabrication and formation of multilevel interconnects. Chemical mechanical polishing (CMP) has emerged recently as a new processing technique for achieving a high degree of planarization for submicron VLSI applications. The polishing process has many variables, and most of which are not well understood. The factors determine the planarization performance are slurry and pad type, insert material, conditioning technique, and choice of polishing tool. Circuit density, pattern size, and wiring layout also affect the performance of a CMP planarization process. This paper presents the results of studies on CMP process window characterization for 0.35 micron process with 5 metal layers.