The thermal behavior of Flow Pattern Defect (FPD) and Large Pit (LP) in Czochralski Silicon crystal was investigated by applying high temperature annealing ($geq$$1100^{circ}C$) and non-agitated Secco etching. For evaluation of the effect of LP upon device performance/yield, commercial DRAM and ASIC devices were fabricated. The results indicated that high temperature annealing generates LPs whereas it decreases FPD density drastically. However, the origins of FPD and LP seemed to be quite different by not showing any correspondence to their density and the location of LP generation and FPD extinction. By not showing any difference between the performance/yield of devices whose design rule is larger than 0.35 $mu extrm{m}$, LP seemed not to have detrimental effects on the performance/yield.