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A Study on the Optimized Copper Electrochemical Plating in Dual Damascene Process
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  • A Study on the Optimized Copper Electrochemical Plating in Dual Damascene Process
  • A Study on the Optimized Copper Electrochemical Plating in Dual Damascene Process
저자명
Yoo. Hae-Young,Chang. Eui-Goo,Kim. Nam-Hoon
간행물명
Transactions on electrical and electronic materials
권/호정보
2005년|6권 5호|pp.225-228 (4 pages)
발행정보
한국전기전자재료학회
파일정보
정기간행물|ENG|
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8;{mu}m$ and $1.0;{mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.