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Design and Fabrication of a Low-cost Wafer-level Packaging for RF Devices
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  • Design and Fabrication of a Low-cost Wafer-level Packaging for RF Devices
  • Design and Fabrication of a Low-cost Wafer-level Packaging for RF Devices
저자명
Lim. Jae-Hwan,Ryu. Jee-Youl,Choi. Hyun-Jin,Choi. Woo-Chang
간행물명
Transactions on electrical and electronic materials
권/호정보
2014년|15권 2호|pp.91-95 (5 pages)
발행정보
한국전기전자재료학회
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정기간행물|ENG|
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{ imes}1.04{ imes}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{ imes}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.