The accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the thrshold voltage shifts of a-Si:H TFT"s may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the stressing periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si:H TFT"s is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.